1. Field of the Invention
The present invention relates to a method for forming a misalignment inspection mark that is suitable for inspection of a fine, large-scale semiconductor integrated circuit, as well as a method for manufacturing a semiconductor device.
2. Description of the Related Art
In a process of manufacturing a semiconductor device, to form device patterns for a plurality of mask levels by means of overlay patterning, a plurality of mask patterns are sequentially laid on top of one another on a semiconductor wafer and then exposed. During exposure, misalignment inspections are carried out to prevent a possible open circuit or leakage between the device pattern in a reference layer and the device pattern in the overlying layer. These inspections check whether or not the reference layer device pattern and the overlying layer device patterns lie correctly on top of one another. Thus, in addition to the device patterns, misalignment inspection marks are formed on a semiconductor wafer to inspect the device patterns for misalignment.
For example, in manufacturing a fine, large-scale semiconductor integrated circuit with a minimum processing size F of at most about 100 to 150 nm, a high-level mask processing technique or photolithography technique is essential. In particular, a further reduction in the size of semiconductor integrated circuits increases the size of misalignment inspection marks relative to that of device patterns. This varies the effect of aberration of the optical system of an exposure apparatus, focal distance, or the like, between the misalignment inspection mark and the device pattern. The varying effect of aberration, focal distance, or the like also varies the amount of transfer misalignment between the misalignment inspection mark and device pattern, which are transferred to the semiconductor wafer. Thus, in spite of the minimized amount of misalignment between the misalignment inspection marks, significant alignment errors may disadvantageously occur between the device patterns.
Moreover, in a conventional method of forming misalignment inspection marks larger than the device patterns in width, on the same mask substrate, the device pattern and the inspection mark have different coverages on the substrate. Accordingly, in view of a possible loading effect during a lithography or dry etching process for fine patterns, the misalignment inspection marks do not enable the fluctuation of the process between the device patterns to be precisely evaluated.
Thus, to equalize the amount of transfer misalignment between the misalignment inspection mark and the device pattern to minimize alignment errors between the device patterns, a method has been proposed which uses misalignment inspection marks having the same size, shape, and the like as those of a device pattern (for example, Jpn. Pat. Appln. KOKAI Publication No. 2002-64055).
However, for example, in a semiconductor storage device, a chip area is mostly occupied by a periodically repeated pattern of memory cells. A further reduction in the size of the memory cell pattern allows an increase in the number of elements periodically integrated in a large chip area. Compared to the memory cell pattern, which can be approximated through such an infinite expanse, the misalignment inspection marks simply having the same line width and the like as those of the device pattern do not serve to faithfully reproduce the device pattern.
Specifically, misalignment inspection marks used in a dicing area around the periphery of the chip area may be composed of a set of a plurality of fine patterns locally formed in an area of a finite width. In this case, the periodicity or uniformity of the pattern arrangement is discontinued at the boundaries (edges) of the area occupied by these misalignment inspection marks. Consequently, these misalignment inspection marks are not optically equivalent to the device pattern. The pattern shape of boundaries (edges) of the misalignment inspection marks may be deformed by aberration or the like and become different from that of the device pattern. This may degrade measurement accuracy of misalignment inspections.